During a two terminal, electrostatic discharge (ESD) event, a large current pulse is injected into one electrical connection or signal pad of an integrated circuit and extracted from another pad, with all other pads floating. Typical current pulses from such events have peak injected currents that exceed one ampere. For an integrated circuit to survive such an event without damage, a robust, low impedance shunt path for the current must be available from any pad to any other pad. In order to avoid interfering with the integrated circuit's normal operation, ESD protection circuitry generally have both active (on) and inactive (off) states. The protection circuit should stay off under normal operating conditions and turn on quickly during an ESD event. It should effectively steer current into the intended shunt path when it is active, but should not interfere with normal operation while in its off state. In particular, the protection circuit coupled to a signal pad must not add excessive resistive or capacitive load to the pad, or add excessively to the noise level of signals applied to the signal pad, or have substantial off-state leakage.
Some functional applications of an integrated circuit require direct connections of input or output (I/0) terminal pads to one or more external buses. These buses may carry active signals even when power is not applied to the integrated circuit. ESD protection circuitry must not interfere with the operation of those buses under those conditions. The directly connected I/0 pads must not draw excessive current when a bus signal is pulled high and power to the integrated circuit is off. Because the buses can carry active signals even when power to an integrated circuit with one or more I/0 pads directly connected to the bus is off, the protection circuitry must maintain a high trigger voltage in power-off conditions. Consequently, the ESD protection circuits must have a trigger voltage that is independent of the supply voltage. Conventional shunt devices, such as silicon controlled rectifiers (SCRs) and field FETs, are triggered by avalanche breakdown or punchthrough above some fixed voltage threshold. These devices require series resistance between the shunt device and the nFET driver of the I/0 pad for reliable protection in many integrated circuit processes. Alternatively, capacitive coupling could be used to lower the trigger voltage of such shunt devices under transient conditions, but, with capacitive coupling, the above-noted requirement for low power-off leakage with signals active would be very difficult to meet.
An object of the invention is to provide an ESD protection circuit for I/0 terminal pads of an integrated circuit with supply voltage independent triggering, meeting low leakage, no series resistance requirements, which is especially adapted for situations where signals-active/power-off ESD protection is needed.
Another object of the invention is to provide such an ESD protection circuit which is also adaptable for use on signals that do not have the signals-active/power-off requirement, so that a diode connection from the signal to the positive power supply bus is tolerable.